Today's computer systems are often mobile. Such mobile computer systems are generally powered by batteries at least some of the time. Users expect to use their mobile computer for a long time without recharging the batteries. Today's mobile computer systems extend battery life by creating more powerful batteries and/or by decreasing power consumption of the mobile computer system. One method of decreasing power consumption in a computer system is to enter a power management mode when the computer is not in use.
A power management mode is a state in which the power consumption of the computer system is decreased. One known prior art power management mode is referred to herein as "suspend." The suspend mode may refer to a number of different states in which power consumption is reduced. However, for the purposes of this application, suspend mode refers to a "deep suspend" in which power is disconnected from at least part of the computer system. The suspend mode allows the computer to "go to sleep," a state in which power consumption is significantly decreased. When the computer is "woken up" from the suspend mode, it is in the same condition as it was prior to suspend. For example, if a user is working on a word processing document when the computer goes to sleep, when the computer wakes up, it displays the same word processing document. Such information is generally stored in dynamic memory, i.e. memory which needs to be refreshed periodically. Logic that is operational during suspend mode is used to refresh the dynamic memory and exit the suspend mode. This logic is referred to herein as suspend logic. The suspend logic is only about 1-3% of the total logic on a chip. Hence, if only the suspend logic is powered, the power consumption of the chip is dramatically reduced. The logic that is not operational during the suspend mode is referred to herein as normal logic.
One prior art method of entering into a power management mode is described below. A computer system includes a processor, a mobile system controller, and a PCI I/O controller. Power management mode is initiated by asserting a suspend-state pin on the mobile system controller, SUS_STAT#. A suspend logic area is isolated, separately powered, and clocked. A PWROK pin indicates the power state of the normal logic. In one embodiment, when the PWROK pin is high, the power to the normal logic is on, and when the PWROK pin is low, the power is shut off. After entering into the suspend mode, the PWROK pin is pulled low, and then power to the normal logic is shut off. At this point, the computer system is in the power management mode, and power is isolated from most components of the computer system. However, power, via a separate power connection, is maintained to the suspend logic.
The suspend logic maintains the dynamic memory and is needed to exit from the power management mode. The suspend logic is connected to normal logic, when the computer system is in a normal mode. Thus, the inputs to the suspend logic have to be isolated from the rest of the computer system while the computer system is in the power management mode. In this way, no false inputs are input to the suspend logic. Not isolating the inputs to the suspend logic could lead to incorrect states in CMOS devices, which can result in leakage, and thus power drains. The PWROK pin is used to isolate inputs from the normal logic to the suspend logic. The state of the PWROK pin is defined to be logic low when the power is off. The inputs to the suspend logic and the PWROK pin are coupled through a logical AND function. Thus, when the PWROK pin is low, no values will be propagated into the suspend logic.
One prior art method of exiting a power management mode is initiated by asserting an external RESET pin on the mobile system controller. The SUS_STAT# pin is deasserted in response, indicating the end of the power management mode. The main power connection is reactivated. After the power supply stabilizes, the PWROK pin is driven high, to indicate that there is a stable power supply. This removes the isolation of the suspend logic from the normal logic.
The prior art methods described above require external pins, including the RESET pin, the PWROK pin, and the SUS_STAT# pin. In most computer systems having sufficient number of pins for external signals is expensive. Therefore, a method that reduces the number of external pins would be advantageous.
Therefore, what is needed is a method and apparatus to enter into and exit out of a power management mode which does not require one or more of the external pins.